Regviz

Espressif Systems /ESP32-P4 /ISP /CNTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CNTL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/ISP/CNTL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MIPI_DATA_EN)MIPI_DATA_EN 0 (ISP_EN)ISP_EN 0 (BLC_EN)BLC_EN 0 (DPC_EN)DPC_EN 0 (BF_EN)BF_EN 0 (LSC_EN)LSC_EN 0 (DEMOSAIC_EN)DEMOSAIC_EN 0 (MEDIAN_EN)MEDIAN_EN 0 (CCM_EN)CCM_EN 0 (GAMMA_EN)GAMMA_EN 0 (RGB2YUV_EN)RGB2YUV_EN 0 (SHARP_EN)SHARP_EN 0 (COLOR_EN)COLOR_EN 0 (YUV2RGB_EN)YUV2RGB_EN 0 (AE_EN)AE_EN 0 (AF_EN)AF_EN 0 (AWB_EN)AWB_EN 0 (HIST_EN)HIST_EN 0 (BYTE_ENDIAN_ORDER)BYTE_ENDIAN_ORDER 0ISP_DATA_TYPE 0ISP_IN_SRC 0ISP_OUT_TYPE

Description

isp module enable control register

Fields

MIPI_DATA_EN

this bit configures mipi input data enable. 0: disable, 1: enable
ISP_EN

this bit configures isp global enable. 0: disable, 1: enable
BLC_EN

this bit configures blc enable. 0: disable, 1: enable
DPC_EN

this bit configures dpc enable. 0: disable, 1: enable
BF_EN

this bit configures bf enable. 0: disable, 1: enable
LSC_EN

this bit configures lsc enable. 0: disable, 1: enable
DEMOSAIC_EN

this bit configures demosaic enable. 0: disable, 1: enable
MEDIAN_EN

this bit configures median enable. 0: disable, 1: enable
CCM_EN

this bit configures ccm enable. 0: disable, 1: enable
GAMMA_EN

this bit configures gamma enable. 0: disable, 1: enable
RGB2YUV_EN

this bit configures rgb2yuv enable. 0: disable, 1: enable
SHARP_EN

this bit configures sharp enable. 0: disable, 1: enable
COLOR_EN

this bit configures color enable. 0: disable, 1: enable
YUV2RGB_EN

this bit configures yuv2rgb enable. 0: disable, 1: enable
AE_EN

this bit configures ae enable. 0: disable, 1: enable
AF_EN

this bit configures af enable. 0: disable, 1: enable
AWB_EN

this bit configures awb enable. 0: disable, 1: enable
HIST_EN

this bit configures hist enable. 0: disable, 1: enable
BYTE_ENDIAN_ORDER

select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]}
ISP_DATA_TYPE

this field configures input data type, 0:RAW8 1:RAW10 2:RAW12
ISP_IN_SRC

this field configures input data source, 0:CSI HOST 1:CAM 2:DMA
ISP_OUT_TYPE

this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/espressif/svd