isp module enable control register
MIPI_DATA_EN | this bit configures mipi input data enable. 0: disable, 1: enable |
ISP_EN | this bit configures isp global enable. 0: disable, 1: enable |
BLC_EN | this bit configures blc enable. 0: disable, 1: enable |
DPC_EN | this bit configures dpc enable. 0: disable, 1: enable |
BF_EN | this bit configures bf enable. 0: disable, 1: enable |
LSC_EN | this bit configures lsc enable. 0: disable, 1: enable |
DEMOSAIC_EN | this bit configures demosaic enable. 0: disable, 1: enable |
MEDIAN_EN | this bit configures median enable. 0: disable, 1: enable |
CCM_EN | this bit configures ccm enable. 0: disable, 1: enable |
GAMMA_EN | this bit configures gamma enable. 0: disable, 1: enable |
RGB2YUV_EN | this bit configures rgb2yuv enable. 0: disable, 1: enable |
SHARP_EN | this bit configures sharp enable. 0: disable, 1: enable |
COLOR_EN | this bit configures color enable. 0: disable, 1: enable |
YUV2RGB_EN | this bit configures yuv2rgb enable. 0: disable, 1: enable |
AE_EN | this bit configures ae enable. 0: disable, 1: enable |
AF_EN | this bit configures af enable. 0: disable, 1: enable |
AWB_EN | this bit configures awb enable. 0: disable, 1: enable |
HIST_EN | this bit configures hist enable. 0: disable, 1: enable |
BYTE_ENDIAN_ORDER | select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} |
ISP_DATA_TYPE | this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 |
ISP_IN_SRC | this field configures input data source, 0:CSI HOST 1:CAM 2:DMA |
ISP_OUT_TYPE | this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565 |